Accessing external data memory (ICEPRO Trace)
Instructions that are accessing data memory have different timing based
on whether the memory is internal or external. For external memory accesses, the timing is again dependent on the number of wait states. This document does not describe the exact timings of these instructions, but they are fairly similar to those described above. It applies to the following instructions: LD (various forms), LDD (various forms), ST (various forms), STD (various forms), LDS, STS, RCALL, ICALL, CALL, RET, RETI, PUSH, POP.
See Also