Simulator I/O Modules

Ports
Ports are simulated as on the real device. This includes the 1.5 clock cycle debouncing delay found in the standard port logic hardware in actual AVR parts. When an I/O module seize control over a pin, the value read from the PINx register is the value generated by that I/O module.

Timer/Counter0
Timer/Counter0 is supported by the Simulator. If a standard device is selected, the Timer/Counter0 overflow interrupt vector and the external counter pin is set accordingly. If a custom device is selected, the Timer/Counter0 overflow interrupt vector and the external counter pin is set as for AT90S1200.

Timer/Counter1
Timer/Counter1 is supported by the Simulator. If a standard device is selected, and the device supports the Timer/Counter1, the Timer/Conter1 interrupt vectors, external counter pin, input capture pin and output pins are set accordingly. For the devices AT90S8515 and AT90S4414, the ICP function is set up on PD4 and the OC1B function is set up on PD6. If a custom device is selected, the Timer/Counter1 will not be present.

Timer/Counter2
Timer/Counter2 is supported by the Simulator. If a standard device is selected, and the device supports the Timer/Counter2, the Timer/Conter2 interrupt vectors, external counter pin and output pins are set accordingly. If a custom device is selected, the Timer/Counter2 will not be present.

UART
The UART is supported by the Simulator. If a standard device is selected, and the device supports the UART, the UART interrupt vectors and the Receive/Transmit pins are set up accordingly. Writing to the UART Data Register (UDR) will not initiate a data transfer. The Data Register must be written by the target application. If a custom device is selected, the UART will not be present.

SPI
The SPI is supported by the Simulator. If a standard device is selected, and the device supports the SPI, the SPI interrupt vector and the SCK/MISO/MOSI/SS pins are set up accordingly. The SPI Data Register shows the SPI receive Register. Editing the SPI Data Register will not initiate a data transfer, even if teh SPI is enabled in Master mode. The Data Register must be written by the target application. If a custom device is selected, the SPI will not be present.

External Interrupts
External interrupts are supported by the Simulator. If a standard device is selected, the external interrupts are set up accordingly. If a custom device is selected, there will be one external interrupt available as for AT90S1200.

EEPROM
The EEPROM is supported by the Simulator. For simplicity, the write timeout has been set to 16 clock cycles, which is significantly shorter than the actual device. If the AT90S1200 or a custom device is selected, the EEPROM write is performed without use of the safety write sequence found in other AVR parts.

EEPROM interrupt
The Eeprom interrupt, WE and WEE are supported by the Simulator. If a custom device is selected, the Eeprom interrupt will not be present.

See Also