; ************************************************************************
;
;    Filename: mode_init.asm
;
;    Date: 07/22/05
;
;    Author: Aaron Garber 
; 
; ***********************************************************************
;
;   License: 
;   
;   This software can be used and modified for personal or non-commercial use only. 
;   
;   Please contact avr.stmd@gmail.com if you wish to use this code
;   for any commercial purpose usage of this software.
;
;   Please contact avr.stmd@gmail.com with any bug fixes or functional improvements.
;                                                                       
;   Use this code at your own risk as there is no guarantee that it will work for you.
;
; ************************************************************************

.org 0x600

; ***** Stepping Initialization ******************************************
; specific initialization depending on mode of stepping selected

init_full_both:

    ; test mode timer interrupt configuration
    ; 200 steps, 1 rev/sec, 1 step per 5 ms
    ; 8Mhz clock -> 125 ns instruction cycle
    ; 5 ms / 125 ns = 40000 counts = 0x9C40
    ldi temp1, 0x9C         
    ldi temp2, 0x40         
    sts OCR1AH, temp1       
    sts OCR1AL, temp2
    
    ldi max_entries, 6            ; 4 entries in step sequence, 2 bytes per entry, zero-based -> 4*2-2=6
    ldi seq_start_H, high(seq_full_both<<1)
    ldi seq_start_L, low(seq_full_both<<1)
    ret

; ************************************************************************

init_full_wave:
    
    ; test mode timer interrupt configuration
    ; 200 steps, 1 rev/sec, 1 step per 5 ms
    ; 8Mhz clock -> 125 ns instruction cycle
    ; 5 ms / 125 ns = 40000 counts = 0x9C40
    ldi temp1, 0x9C         
    ldi temp2, 0x40         
    sts OCR1AH, temp1       
    sts OCR1AL, temp2
    
    ldi max_entries, 6            ; 4 entries in step sequence, 2 bytes per entry, zero-based -> 4*2-2=6
    ldi seq_start_H, high(seq_full_wave<<1)
    ldi seq_start_L, low(seq_full_wave<<1)
    ret

; ************************************************************************

init_half:
    
    ; test mode timer interrupt configuration
    ; 400 steps, 1 rev/sec, 1 step per 2.5 ms
    ; 8Mhz clock -> 125 ns instruction cycle
    ; 2.5 ms / 125 ns = 20000 counts = 0x4E20
    ldi temp1, 0x4E         
    ldi temp2, 0x20         
    sts OCR1AH, temp1       
    sts OCR1AL, temp2
    
    ldi max_entries, 14           ; 8 entries in step sequence, 2 bytes per entry, zero-based -> 8*2-2=14
    ldi seq_start_H, high(seq_half<<1)
    ldi seq_start_L, low(seq_half<<1)
    ret

; ************************************************************************

init_quarter:
    
    ; test mode timer interrupt configuration
    ; 800 steps, 1 rev/sec, 1 step per 1.25 ms
    ; 8Mhz clock -> 125 ns instruction cycle
    ; 1.25 ms / 125 ns = 10000 counts = 0x2710
    ldi temp1, 0x27         
    ldi temp2, 0x10         
    sts OCR1AH, temp1       
    sts OCR1AL, temp2
    
    ldi max_entries, 30           ; 16 entries in step sequence, 2 bytes per entry, zero-based -> 16*2-2=30
    ldi seq_start_H, high(seq_quarter<<1)
    ldi seq_start_L, low(seq_quarter<<1)
    ret

; ************************************************************************

init_sixth:
    
    ; test mode timer interrupt configuration
    ; 1200 steps, 1 rev/sec, 1 step per 0.833 ms
    ; 8Mhz clock -> 125 ns instruction cycle
    ; 0.833 ms / 125 ns = 6666.7 counts = 0x1A0B
    ldi temp1, 0x1A         
    ldi temp2, 0x0B         
    sts OCR1AH, temp1       
    sts OCR1AL, temp2
        
    ldi max_entries, 46           ; 24 entries in step sequence, 2 bytes per entry, zero-based -> 24*2-2=46
    ldi seq_start_H, high(seq_sixth<<1)
    ldi seq_start_L, low(seq_sixth<<1)
    ret

; ************************************************************************

init_eighth:
    
    ; test mode timer interrupt configuration
    ; 1600 steps, 1 rev/sec, 1 step per 0.625 ms
    ; 8Mhz clock -> 125 ns instruction cycle
    ; 0.625 ms / 125 ns = 5000 counts = 0x1388
    ldi temp1, 0x13         
    ldi temp2, 0x88         
    sts OCR1AH, temp1       
    sts OCR1AL, temp2

    ldi max_entries, 62           ; 32 entries in step sequence, 2 bytes per entry, zero-based -> 32*2-2=62
    ldi seq_start_H, high(seq_eighth<<1)
    ldi seq_start_L, low(seq_eighth<<1)
    ret

; ************************************************************************

init_tenth:
    
    ; test mode timer interrupt configuration
    ; 2000 steps, 1 rev/sec, 1 step per 0.5 ms
    ; 8Mhz clock -> 125 ns instruction cycle
    ; 0.5 ms / 125 ns = 4000 counts = 0xFA0
    ldi temp1, 0xF        
    ldi temp2, 0xA0         
    sts OCR1AH, temp1       
    sts OCR1AL, temp2
    
    ldi max_entries, 78           ; 40 entries in step sequence, 2 bytes per entry, zero-based -> 40*2-2=78
    ldi seq_start_H, high(seq_tenth<<1)
    ldi seq_start_L, low(seq_tenth<<1)
    ret

; ************************************************************************

init_twelfth:                 
        
    ; test mode timer interrupt configuration
    ; 2400 steps, 1 rev/sec, 1 step per 0.417 ms
    ; 8Mhz clock -> 125 ns instruction cycle
    ; 0.417 ms / 125 ns = 3333.3 counts = 0xD05
    ldi temp1, 0xD         
    ldi temp2, 0x05         
    sts OCR1AH, temp1       
    sts OCR1AL, temp2

    ldi max_entries, 94           ; 48 entries in step sequence, 2 bytes per entry, zero-based -> 48*2-2=94
    ldi seq_start_H, high(seq_twelfth<<1)
    ldi seq_start_L, low(seq_twelfth<<1) 
    ret

; ************************************************************************

init_sixteenth:                 
        
    ; test mode timer interrupt configuration
    ; 3200 steps, 1 rev/sec, 1 step per 0.3125 ms
    ; 8Mhz clock -> 125 ns instruction cycle
    ; 0.3125 ms / 125 ns = 2500 counts = 0x9C4
    ldi temp1, 0x9         
    ldi temp2, 0xC4         
    sts OCR1AH, temp1       
    sts OCR1AL, temp2

    ldi max_entries, 126          ; 64 entries in step sequence, 2 bytes per entry, zero-based -> 64*2-2=126
    ldi seq_start_H, high(seq_sixteenth<<1)
    ldi seq_start_L, low(seq_sixteenth<<1)
    ret

; ************************************************************************